 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. october 2015 docid028515 rev 1 1/58 stcom powerline communication and application system-on-chip datasheet - production data features ? integrated differential plc analog front-end ? pga with automatic gain control and adc ? current dac with transmission predriver ? digital transmissi on level control ? zero crossing comparator ? up to 500 khz plc signal bandwidth ? integrated dual line driver ? 14 v p-p single ended, 28 v p-p differential output range ? very high linearity for emc compliance ? externally configurable amplifier topology ? 1 a rms max. current ? embedded overtemperature protection ? suitable for all plc signals up to 500 khz ? fully reprogrammable real-time engine (rte) modem for plc standards up to 500 khz ? integrated application core: arm ? 32-bit cortex?-m4f cpu ? 96 mhz maximum frequency ? 8-channel direct memory access controller ? 8-region memory protection unit ? serial wire and jtag interfaces ? cortex-m4 embedded trace macrocell? ? up to 86 multiplexed gpios ? 11 timers ? 1 flexible crc calculation unit ? 5 usarts (iso 7816 compliant), 5 spi, 3 i 2 c ? 12-bit general purpose adc with 6 channels ? cryptographic engine ? aes 128/192/256 engine ? true random number generator ? memories ? 640 kb or 1 mb of embedded flash ? 128 kb of embedded sram ? 8 kb of embedded shared ram ? flexible static memory controller ? clock management ? 24 mhz external crystal for system clock with internal qfs synthesizer ? 32.768 khz external crystal for rtc ? power management ? 3.3 v and 8 - 18 v external supply voltages ? 1.2 v and 5 v integrated linear regulators ? normal and low power modes ? real-time clock (rtc) ? vbat supply with battery health monitoring for rtc and backup registers ? -40 c to +85 c operating temperature range applications ? smart metering, smart grid and ?internet of things? applications ? compliant with cene lec, fcc, arib regulations tqfp176 (20 x 20 x 1 mm) www.st.com
contents stcom 2/58 docid028515 rev 1 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 power line communication (plc) sub-system . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 real-time engine (rte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.2 digital front-end (dfe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3 analog front-end (afe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.4 line driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 application core sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.1 arm ? cortex?-m4f core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.2 floating point unit (fpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.3 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 11 1.3.4 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3.5 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3.6 debug and trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3.7 general purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3.8 multi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.9 timers and watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.10 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 18 1.3.11 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 cryptographic engine (cryp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.1 true random number generator (trng) . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4.2 pseudo random number generator (prng) . . . . . . . . . . . . . . . . . . . . . 19 1.5 interprocessor communication (ipc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.6 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6.1 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6.2 one-time programmable (otp) section . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6.3 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6.4 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . 21 1.7 reset, control, clock generation (rcc) and system controller (sys_ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.8 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 vbat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 docid028515 rev 1 3/58 stcom contents 58 1.9 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.10 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 27 1.11 temperature sensors and overtemperature protection . . . . . . . . . . . . . . 28 1.12 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.13 system reprogrammability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.13.1 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.13.2 in-application programming (iap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.1 pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.2 gpios multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.4 plc analog front-end (afe) and line driver characteristics . . . . . . . . . . . 50 4.4.1 line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.4.2 line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.4.3 afe characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.5 embedded flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 tqfp176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 list of tables stcom 4/58 docid028515 rev 1 list of tables table 1. cortex?-m4f core configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. interrupt definition and position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. dma channels muxing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. embedded flash sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. boot mode and security level rela tionship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. boot modes and boot0/1 pin values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 7. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8. gpios multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. absolute maximum ratings - voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 table 10. absolute maximum ratings - current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 11. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. analog supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 13. digital supply characteristics - rte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 14. digital supply characteristic s - cortex?-m4 fetching from ram . . . . . . . . . . . . . . . . . . . . 47 table 15. digital supply characteristic s - cortex?-m4 fetching data from eflash . . . . . . . . . . . . . . . 47 table 16. digital supply characteristic s - doze (sleep)/deepsleep mode . . . . . . . . . . . . . . . . . . . . . 47 table 17. supply characteristics - qfs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 18. 24 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 19. 32 khz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. digital supply characteristics - i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. digital supply characteristic s - power consumption under battery . . . . . . . . . . . . . . . . . . . 49 table 23. line driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. predriver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. receiver input referred noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. plc pga characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. zero crossing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 31. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. flash memory current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. tqfp176 (20 x 20 x 1 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 34. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 35. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 docid028515 rev 1 5/58 stcom list of figures 58 list of figures figure 1. stcom basic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. stcom detailed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. reset, clock and system controlle r interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. stcom clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5. power supply scheme - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6. power supply scheme - plc afe and line driver sect ion. . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. tqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 9. line driver test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 10. tqfp176 (20 x 20 x 1 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 description stcom 6/58 docid028515 rev 1 1 description the stcom is a device that integrates a power line communication (plc) modem and a high-performance application core. the plc modem architecture has been designed to target en50065, fcc, arib compliant plc applications. together with the applicatio n core, it enables the stcom to support the prime, g1, g3, ieee 1901.2, meters and more ? and other narrow band plc protocol specifications. the stcom basic block diagram is shown in figure 1 . figure 1. stcom basic block diagram % v b m m j o f e s j w f s $ v s s f o u d p o u s p m 5 i f s n b m q s p u f d u j p o 1 - $ " ' & 3 f b m u j n f t v c t z t u f n 3 " . 3 5 & 1 s p u p d p m b o e b q q m j d b u j p o t v c t z t u f n 3 " . " 3 . $ p s u f y . ' m b t i 3 5 $ 3 $ $ b o e t z t u f n 1 f s j q i f s b m t 1 p x f s n b o b h f n f o u & y u f s o b m o f u x p s l 1 " @ 0 6 5 1 " @ 0 6 5 $ 4 ' 3 9 @ * / 1 3 9 @ * / / ; $ @ * / 1 " @ * / 1 " @ * / 5 9 % 3 7 @ 0 6 5 1 5 9 % 3 7 @ 0 6 5 / 7 7 7 7 7 # " 5 0 4 $ @ 0 6 5 0 4 $ @ * / . $ - , @ 0 6 5 . $ - , @ * / # 0 0 5 # 0 0 5 3 & 4 & 5 @ / 3 5 $ @ 5 " . 1 " 3 5 $ @ 5 " . 1 # " . docid028515 rev 1 7/58 stcom description 58 1.1 device architecture the architecture is composed of the following parts: 1. plc front-end including digital front-end and analog front-end 2. plc line driver 3. real-time engine: the digital core running the lower layers of the plc protocol stack and implementing modulation and demodulation 4. protocol engine: the main digital core for running the upper layers of the plc protocol stack 5. wide range of peripherals logically divided into 4 blocks: ? basic peripherals ? com1 peripherals ? com2 peripherals ? crypto peripherals. the stcom detailed architecture is shown in figure 2 . description stcom 8/58 docid028515 rev 1 figure 2. stcom detailed architecture " ) # 4 3 " . % . " $ d i b o o f m t ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 ( 1 * 0 * 1 $ 4 i b s f e 3 " . ' 4 . $ " ) # " 1 # " ) # " 1 # " 1 # " 1 # 5 3 / ( $ 3 $ " & 4 * $ " ) # " 1 # " 1 # ( 1 5 ( 1 5 ( 1 5 ( 1 5 ( 1 5 ( 1 5 ( 1 5 ( 1 5 8 8 % ( 3 5 $ ' - " 4 ) $ 5 3 - ' 4 . $ @ $ 5 3 - 4 : 4 $ 5 3 - 3 $ ( 6 4 " 3 5 6 4 " 3 5 $ " / * $ " % $ " 5 4 1 * 4 1 * 4 1 * 4 1 * 4 1 * " 5 * $ $ " / 6 4 " 3 5 6 4 " 3 5 . * 4 $ " 5 5 $ 5 3 - ' m b t i " 5 5 3 f b m u j n f f o h j o f " ' & 4 3 " . % " $ " % $ $ p n $ p n # b t j d $ s z q u p # b t j d $ 1 6 $ p s u f y . ' ' 1 6 . 1 6 / 7 * $ 4 8 + 5 " ( & 5 . 5 1 * 6 5 i f s n b m - j o f e s j w f s 5 i f s n b m ; f s p d s p t t j o h 1 3 / ( 6 4 " 3 5 " ) # " 1 # " 1 # $ v s s f o u " . docid028515 rev 1 9/58 stcom description 58 1.2 power line communic ation (plc) sub-system the stcom device embeds a full narrow band power line communication (nb-plc) sub- system, comprising the rte, dfe, afe and line driver. the afe and line driver have been designed for a differential power line interface; however, single-ended operation is possible for simpler hardware application development. the dc to 500 khz signal bandwidth is sup ported, targeting a number of possible nb-plc solutions. 1.2.1 real-time engine (rte) to match a performance required by emer ging nb-plc standards, the stcom embeds a proprietary dedicated reprogrammable machine, the real-time engine. it is able to address specific functionalities exploited by ofdm a nd the ones adopted in the current and future nb- plc standards in an efficient way. 1.2.2 digital front-end (dfe) transmission and reception filter chains the dfe includes programmable transmission/recepti on digital filter chains to fit the signal bandwidth in different plc modulation cases. the adc and dac clock frequencies are controlled by the dfe to get the right sample rate fitting the filter chain configuration. automatic gain control (agc) the dfe implements the automatic gain contro l (agc) block for the pga, whose purpose is to adapt the signal to the adc dynamic. current control (cc) the dfe includes also the current control (cc) block for the line driver to limit the maximum output current. 1.2.3 analog front-end (afe) receiving chain the stcom afe features a programmable gain amplifier (pga) and a dedicated analog-to- digital converter (adc) to achieve high rx sensitivity and a wide input range. transmission chain the transmitted signal, generated in the digita l domain, is fed into a dedicated digital-to- analog converter (dac). the dac output is then fed into a predrive r for buffering and applying an additional gain before the line driver. description stcom 10/58 docid028515 rev 1 zero crossing comparator the mains line zero crossing can be detected by providing a mains synchronous bipolar (ac) signal at the input of this comparator. the zero crossing comparator provides positive and negative event information (rising/falling edge or high/low level). 1.2.4 line driver the stcom is equipped with an integrated high -performance dual power line driver. it has very low distortion, allowing the device to comply with emc requirements. when supplied at maximum voltage, the line driver is capable to provide 28 v p-p in differential configuration or 14 v p-p in single-ended configuration. the output current can reach 1 a rms in both differential and single-ended configurations, in order to drive very low power line impedance. any overtemperature event will fo rce the line driver to shut down, thus preventing the stcom to get damaged. 1.3 application core sub-system 1.3.1 arm ? cortex?-m4f core the cortex?-m4 processor is built on a high-performance processor core, with a 3-stage pipeline harvard architecture, making it ideal for demanding embedded applications. the processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high end processing hardware including ieee754- compliant single precision (32-bit) floating point computation, a range of a single cycle and simd multiplication and multip ly with accumulate capabilitie s, saturating arithmetic and dedicated hardware division. to facilitate the design of cost-sensitive dev ices, the cortex?-m4 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handlin g and system debug capa bilities. the cortex?-m4 processor implements a version of the thumb ? instruction set based on thumb-2 ? technology, ensuring high code density and reduced program memory requirements. the cortex?-m4 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. the cortex?-m4 processor provides multiple interfaces using amba? technology to provide high-speed, low latency memory accesses. it supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe boolean data handling. docid028515 rev 1 11/58 stcom description 58 1.3.2 floating point unit (fpu) the fpu fully supports single precision add, subtract, multiply, divide, multiply and accumulate, and square root operations. it al so provides conversi ons between the fixed point and floating point data formats, an d floating point constant instructions. the fpu provides floating point operations that are compliant with the nsi/ieee std 754- 2008 a, ieee standar d for binary floati ng-point arithmetic ? , referred to as the ieee 754 standard. the fpu contains 32 single precision extension registers, which can al so be accessible as 16 double word registers for load, store, and move operations. 1.3.3 nested vectored interrupt controller (nvic) the stcom embeds a nvic able to handle 80 maskable interrupts. the software priority level is configurable in the range of 0 - 31 for each interrupt. a higher level corresponds to a lower priority, so the level 0 is the highest interrupt priority. in case two or more interrupt lines share the same softwa re priority level, the hardware priority level, which is described in table 2 , is used. table 1. cortex?-m4f core configuration component presence comment jtag yes full-featured debug access port (dap), swj-dp and ahb access port etm yes embedded trace macrocell present itm yes instrumentation trace macrocell tpiu yes trace port unit interface present fpb yes flash patch breakpoint dwt yes data watchpoint and trace debug level n/a full debug with data matching for watchpoint generation irq n/a 80 irq source priority level n/a set to 5:32 levels mpu yes memory protection unit present. 8 regions implemented fpu yes floating point unit present (single precision) bb yes bit banding region present reset_all_regs yes reset all synchronous state clkgate yes possibility to minimize dynamic power dissipation by clock gating wic yes 10 lines: nmi, wwdg, rtc, gpio s, ipc, dma, gpt0, spi0 and usart0 description stcom 12/58 docid028515 rev 1 table 2. interrupt definition and position position priority ac ronym description - -3 reset reset - -2 nmi wake-up interrupt - non ma skable interrupt - system error - -1 hardfault all class of fault - 0 memmanage mpu mismatch - 1 busfault prefetch faul t, memory access fault - 2 usagefault undefined instruction or illegal state - 3 svcall system service call via swi instruction - 4 debugmonitor debug monitor - 5 pendsv pendable request for system service - 6 systick system tick timer 0 7 wdg_wic wake-up interrupt - window watchdog 1 8 rtc_wic wake-up interrupt - rtc interrupts 2 9 - reserved 3 10 gpio_wic wake-up interru pt - gpio interrupts 4 11 ipc_wic wake-up interrupt - ipc interrupts 5 12 dmac_wic wake-up inte rrupt - dmac interrupts 6 13 gpt0_wic wake-up interrupt - gpt0 global interrupt 7 14 spi0_wic wake-up interrupt - spi0 global interrupt 8 15 usart0_wic wake-up interrupt - usart0 global interrupt 916 - reserved 10 17 tamper tamper pin interrupt 11 18 rtc real-time clock 12 19 flash_fatal_error flash interface 13 20 flash_ecc_rww_error flash interface 14 21 flash_ary_done flash interface 15 22 ipc_mbox ipc mailbox 16 23 ipc_queues ipc queues 17 24 ipc_sharedram ipc shared memory 18 25 dma_ch(1) dma global interrupt channel 1 19 26 dma_ch(2) dma global interrupt channel 2 20 27 dma_ch(3) dma global interrupt channel 3 21 28 dma_ch(4) dma global interrupt channel 4 22 29 dma_ch(5) dma global interrupt channel 5 23 30 dma_ch(6) dma global interrupt channel 6 24 31 dma_ch(7) dma global interrupt channel 7 docid028515 rev 1 13/58 stcom description 58 25 32 dma_ch(8) dma global interrupt channel 8 26 33 adc adc global interrupt 27 34 - reserved 28 35 - reserved 29 36 fsmc_fill_fifo fsmc interface 30 37 spi1 spi1 global interrupt 31 38 spi2 spi2 global interrupt 32 39 spi3 spi3 global interrupt 33 40 spi4 spi4 global interrupt 34 41 i2c0_event i2c0 global event interrupt 35 42 i2c0_error i2c0 global error interrupt 36 43 i2c1_event i2c1 global event interrupt 37 44 i2c1_error i2c1 global error interrupt 38 45 i2c2_event i2c2 global event interrupt 39 46 i2c2_error i2c2 global error interrupt 40 47 at0_brk advanced timer 0 - brk 41 48 at0_up advanced timer 0 - update 42 49 at0_trg_com advanced timer 0 - trigger and commutation (com) 43 50 at0_cc advanced timer 0 - 4 capcom 44 51 at1_brk advanced timer 1 - brk 45 52 at1_up advanced timer 1 - update 46 53 at1_trg_com advanced timer 1 - trigger and commutation (com) 47 54 at1_cc advanced timer 1 - 4 capcom 48 55 gpt1 gpt1 - global interrupt 49 56 gpt2 gpt2 - global interrupt 50 57 gpt3 gpt3 - global interrupt 51 58 usart1 usart1 global interrupt 52 59 usart2 usart2 global interrupt 53 60 usart3 usart3 global interrupt 54 61 usart4 usart4global interrupt 55 62 can0 can0 global interrupt 56 63 can1 can1 global interrupt 57 64 aes aes global interrupt 58 65 gpio00 gpio00 global interrupt 59 66 gpio01 gpio01 global interrupt table 2. interrupt definition and position (continued) position priority ac ronym description description stcom 14/58 docid028515 rev 1 1.3.4 dma controller (dma) the stcom embeds 1 general purpose dual por t dma controller with 8 channels. it is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. it features dedicated fifos fo r apb/ahb peripherals, a supports burst transfer and is designed to provide the maximum peripheral bandwidth (ahb/apb). the dma controller supports circular buffer management, so that no specific code is needed when the controller reaches the end of the buf fer. it also has a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. each channel is connected to dedicated hardware dma requests, with support for a software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. 60 67 gpio02 gpio02 global interrupt 61 68 gpio03 gpio03 global interrupt 62 69 gpio04 gpio04 global interrupt 63 70 gpio05 gpio05 global interrupt 64 71 gpio06 gpio06 global interrupt 65 72 gpio07 gpio07 global interrupt 66 73 gpio08 gpio08 global interrupt 67 74 gpio09 gpio09 global interrupt 68 75 gpio10 gpio10 global interrupt 69 76 gpt4 gpt4 - global interrupt 70 77 gpt5 gpt5 - global interrupt 71 78 gpt6 gpt6 - global interrupt 72 79 gpt7 gpt7 - global interrupt 73 80 - reserved 74 81 - reserved 75 82 - reserved 76 83 - reserved 77 84 - reserved 78 85 - reserved 79 86 - reserved table 2. interrupt definition and position (continued) position priority ac ronym description docid028515 rev 1 15/58 stcom description 58 table 3. dma channels muxing scheme peripheral ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 (1) adc adc spi0 spi0_tx spi0_rx spi1 spi1_tx spi1_rx spi2 spi2_tx spi2_rx spi3 spi3_tx spi3_rx spi4 spi4_tx spi4_rx usart0 usart0_tx usart0_rx usart1 usart1_tx usart1_rx usart2 usart2_tx usart2_rx usart3 usart3_tx usart3_rx usart4 usart4_tx usart4_rx i2c0 i2c0_tx i2c0_rx i2c1 i2c1_tx i2c1_rx i2c2 i2c2_tx i2c2_rx at0 at0_ch1 at0_ch2 at0_ch4 at0_trig at0_com at0_up at0_ch3 at1 at1_ch3 at1_trig at1_com at1_up at1_ch1 at1_ch2 at1_ch4 gpt0 gpt0_up gpt1 gpt1_up gpt2 gpt2_up gpt3 gpt3_up gpt4 gpt4_up gpt5 gpt5_up gpt6 gpt6_up gpt7 gpt7_up 1. channel 8 is reserved. description stcom 16/58 docid028515 rev 1 1.3.5 memory protection unit (mpu) the mpu divides the memory map into up to 8 regions, and defines the location, size, access permissions, and memory attri butes of each region. it supports: ? independent attribute settings for each region ? overlapping regions ? export of memory attr ibutes to the system. ? background region when memory regions overlap, memory access is affected by the attributes of the region with the highest number. the background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. the mpu is useful to isolate and protect differ ent parts of the firmware by giving different levels of access privileges. if a part of the firm ware tries to access a memory location that is prohibited by the mpu, the processor generates a fault. this causes a fault exception that could be detected by the privileged firmware, which can take the appropriate action. the mpu is optional and can be bypassed for applications that do not need it. 1.3.6 debug and trace serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. embedded trace macrocell? (etm) the arm embedded trace macroce ll provides greater visibility of the instruction and data flow inside the cortex?-m4 core by streaming compressed data at a very high rate from the stcom device through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is then connected to a host in order to record and then format the information for displaying and analysis. 1.3.7 general purpose input/outputs (gpios) the stcom device has 11 gpios ports named fr om gpio00 to gpio10. each port is able to manage 8 pins, except the gpio08 port that manages 6 pins. each gpio pin can be individually configured by software as output (push-pull or open drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate functions (with or wit hout pull-up or pull-down). each gpio pin can also generate interrupt depending on a level (low and high), or a transactional value of the pin (rising or falling edge). external interrupt each gpios port can generate interrupts. for ea ch port one interrupt line is dedicated. the pins of one port share the same interrupt line. docid028515 rev 1 17/58 stcom description 58 1.3.8 multi-ahb bus matrix the 32-bit multi-ahb bus matrix interconnects all the masters (cortex?-m4, dma, and real- time engine) and the slaves (flash memory, ram, ah b and apb peripherals, and real-time engine) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. 1.3.9 timers and watchdog the stcom embeds 8 general purpose timers, two advanced timers and one window watchdog. the cortex?-m4 is also equipped with a systick timer. general purpose timer (gpt) the stcom device includes 8 full-featured general purpose timers based on a 16-bit autoreload up/down counter and a 16-bit programmable prescaler. advanced timers (at) the stcom includes 2 advanced-control ti mers based on a 16-bit autoreload up/down counter driven by a 16-bit programmable presca ler. they all feature 4 independent channels for input capture, output compare, pwm generation or one pulse mode output. it may be used for a variety of purposes, in cluding measuring the pulse lengths of input signals (input capture) or generating ou tput waveform s (output compare, pwm, complementary pwm with deadtime insertion). window watchdog (wwdg) the window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by un foreseen logical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates a device reset on expiry of a programmed ti me period, unless the program refreshes the contents of the down counter register. a device reset is also generated if the down counter value is refreshed before the down counter has reached the proper window register value. this implies that the counter must be refreshed in a limited window. the window watchdog is based on a 7-bit free-running down counter with two conditional resets: the down counter is reloaded outside the window or the down counter value becomes less than 0x40. the window watchdog supports early wake-up interrupt trigged when the down counter is equal to 0x40. systick timer the cortex?-m4 has a 24-bit system timer, systick, which counts down from the programmable reload value to zero. it supports the autoreload and can generate a maskable system interrupt when the counter reaches zero. description stcom 18/58 docid028515 rev 1 1.3.10 crc (cyclic redund ancy check) calculation unit the cyclic redundancy check (crc) is a widely used method for detecting errors. the crc calculation unit is used to get a crc code in a flexible way using a co nfigurable polynomial. output data size can be selected between 8, 16, 24 or 32 bits. input data size can be configured between 1, 8, 16, 24 or 32 bits with selectable bit and byte endianness. the crc unit allows the specificat ion of the initial value (all zero , all one, or a generic value) and the possibility to select an automatic xo r with all one when read ing the data output. 1.3.11 communication interfaces inter-integrated circuit interface (i 2 c) the stcom embeds 3 i 2 c bus interfaces that can operate in multimaster and slave modes. they can support the standard and fast modes. they support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave) . a hardware crc genera tion/verification is embedded. the i 2 c peripherals can be served by dma and support smbus 2.0/pmbus? operations. universal synchronous/asynchronous receiver transmitters (usart) the stcom embeds 5 universal synchronous /asynchronous receiv er transmitters. these five interfaces provide asynchronous communication, irda ? sir endec support, a multiprocessor communication mode, single-wire half-duplex communication mode and have an lin master/slave capability. the peripherals also provide hardware management of the cts and rts signals, a smartcard mode (iso 7816 compliant) and a spi-like communication capability. all interfaces can be served by the dma controller. serial peripheral interface (spi) the stcom embeds 5 spis in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card?/mmc? modes. all spis can be served by the dma controller. the spi interface can be configured to o perate in a ti? mode for communications in master mode and slave mode. controller area network (can) the stcom embeds 2 can modules able to perform communication according to the can protocol version 2.0 part a and b. the bitrate can be programmed to values up to 1 mbit/s. for communication on a can network, individual message objects are configured. each message object has its own identifier mask. the message obje cts and identifier masks are stored in the 256 byte size message ram with a programmable fifo mode. all functions concerning the handling of messages are implemented in the message handler. those functions are the accept ance filtering, the transfer of messages between the can core and the message ram, and the handling of transmission requests as well as the generation of the module interrupt. docid028515 rev 1 19/58 stcom description 58 general purpose analog-to-digital converter (adc) one 12-bit sar adc working at a maximum conv ersion rate of 2 msps is embedded in the stcom. the adc has 6 external available input channels performing conversion in a single, continuous or scan mode. the core accesses to the peripheral through a 4x12-bit fifo interface. the adc can be served by the dma controller. additional 2 channels are internally used to monitor the vbat and the low power temperature sensor. 1.4 cryptographic engine (cryp) the stcom embeds an advanc ed hardware aes pe ripheral which implements an advanced standard cryptographic algorithm a ccording to the nist fips 197. the block processes 128-bit data blocks using a key with the following possible sizes: 128, 192, 256 bits. the peripheral also supports the following modes: ?electronic code book? (ecb), ?cipher block chaining? (cbc), ?counter ?mode (ctr), ?galois/counter mode? (gcm), gmac and ccm modes. the peripheral is able to encrypt and decrypt data. interrupt can be generated when one operation is finished. 1.4.1 true random number generator (trng) the stcom embeds a trng processor based on a continuous analog noise that provides a random 16-bit value. to avoid pseudo random sequences, two consecutive accesses have to be performed when the ready bit in the status register is set to 1. 1.4.2 pseudo random num ber generator (prng) the stcom embeds a prng processor that prov ides a pseudo random 32-bit value. initial seed can be configured by software. 1.5 interprocessor communication (ipc) the cortex?-m4 core and the real-time engine communicate by means of an additional 8 kbyte shared static ram. this memory can be accessed by the two cores through an interprocessor communication block that gu arantees coherent and consistent read and modify operations, to provi de several functionalities to the system, among the others: ? configuration of real-time engine modes an d functionalities during the normal working operations ? data and information exchange between the cortex?-m4 and real-time engine in both directions. ? the cortex?-m4 wake up from a low power mode triggered by the real-time engine. the real-time engine wakes up from a low power mode triggered by the cortex?-m4. description stcom 20/58 docid028515 rev 1 1.6 memories 1.6.1 embedded flash memory the embedded flash has the following features: ? 640 kb or 1 mb of size ? 128-bit wide data read ? 64-bit data write through a double 32-bit bus write ? sector erase with possibility to suspend erase procedure in case of read access to other flash sectors ? multiple sector erase. shadow sector is accessible only in some security levels (see section 1.12: boot modes on page 28 ). 1.6.2 one-time program mable (otp) section the stcom embeds a one-time programmable (otp) section in the shadow sector of the embedded flash memory. during the manufactur ing process, the eui48 is stored in this section. the user can also write its private ke y used during the boot process to verify and authenticate the firmware image. this otp se ction can be configured to avoid reads by firmware in order to protect user confidential information (see section 1.12 ). table 4. embedded flash sectors block name number base address size note main memory b0f0 0 0x00000000 16 kb b0f1 1 0x00004000 16 kb b0f2 2 0x00008000 32 kb b0f3 3 0x00010000 32 kb b0f4 4 0x00018000 16 kb b0f5 5 0x0001c000 16 kb b0f6 6 0x00020000 64 kb b0f7 7 0x00030000 64 kb b0f8 8 0x00040000 128 kb b0f9 9 0x00060000 128 kb b0fa 10 0x00080000 128 kb not available in stcom05 b0fb 11 0x000a0000 128 kb not available in stcom05 b0fc 12 0x000c0000 128 kb not available in stcom05 b0fd 13 0x000e0000 128 kb shadow sector b0sh 14 0x00100000 16 kb docid028515 rev 1 21/58 stcom description 58 1.6.3 embedded sram the stcom device has 128 kb of a static ram. the cortex?-m4 can perform byte, half word (16 bits) or full word (32 bits) access to the sram at maximum speed, with zero wait states for both read and write operations. t he sram start address is 0x20000000, the end address is 0x20001ffff. the sram is split into two blocks of 64 kb with a capability for concurrent access by ahb master sub-systems. the cortex?-m4 can also execute a code from the ram at a zero wait state. 1.6.4 flexible static memory controller (fsmc) the stcom embeds a fsmc peripheral able to interface external memory devices. the types of memory supported are: ? asynchronous parallel nor flash with up to 21-bit address bus (no synchronous parallel nor supported) ? asynchronous sram memories the data bus can be selected between 16 bits or 8 bits (reducing the total amount of accessible memory), for littl e or big endian operation. the fsmc peripheral can connect up to 2 memo ries with 2 independent chip select lines (ebar). the maximum size of each memory is 4 mb. having 2 chip select lines, the maximum external memory size is 8 mb. description stcom 22/58 docid028515 rev 1 1.7 reset, control, cl ock generation (rcc) and system controller (sys_ctrl) all the clock and reset configuration regi sters are located in the misc and sysctrl blocks. figure 3 shows the interaction between these blocks. figure 3. reset, clock and system controller interaction the system reset is generat ed by the resetn pin (activ e low). through the system controller is also possible to a ssert a system software reset. the software re set to single peripherals can be forced through misc registers. 6 < 6 b & 7 5 / 0 , 6 & 4 ) 6 5 h v h w d q g f o r f n v & o r f n v 5 h v h w v $ 0 docid028515 rev 1 23/58 stcom description 58 clock management two external clock sources are required for the stcom: 1. 24 mhz frequency 2. 32.768 khz frequency internal clocks are generated by a quadruple frequency synthesi zer (qfs) that is fed by the 24 mhz source. digital blocks can also use the external sources as clock reference. the clock strategy is depicted in figure 4 . figure 4. stcom clock tree . $ - , @ * / . $ - , @ 0 6 5 0 4 $ @ * / 0 4 $ @ 0 6 5 , ) [ 0 4 $ $ m p d l h b u j o h d f m m f o b c m f t f m f d u p s 4 : 4 $ 5 3 9 5 " - 3 2 4 8 p s . * 4 $ ( & / @ $ - , @ $ ' ( < > . ) [ 0 4 $ % * 7 . * 4 $ " . # " @ $ ' ( < > . * 4 $ 0 4 $ * @ $ ' ( < > 2 ' 4 . * 4 $ 2 ' 4 @ $ 5 3 < > . * 4 $ 2 ' 4 @ $ 5 3 . * 4 $ 2 ' 4 @ $ - , @ $ 5 3 . * 4 $ 2 ' 4 @ $ - , @ $ 5 3 . * 4 $ 2 ' 4 @ $ - , @ $ 5 3 . * 4 $ 2 ' 4 @ $ - , @ $ 5 3 4 : 4 $ 5 3 1 - - 3 2 4 8 ) $ - , u p " ) # q f s j q i f s b m t d q v @ g d m l d q v @ i d m l d q v @ t u d m l $ 1 6 4 5 $ - , e j w j t p s 1 $ - , @ # u p c b t j d q f s j q i f s b m t # b t j d " 1 # q s f t d b m f s 1 $ - , @ $ u p $ p n q f s j q i f s b m t $ p n " 1 # q s f t d b m f s 1 $ - , @ $ u p $ p n q f s j q i f s b m t $ p n " 1 # q s f t d b m f s 1 $ - , @ $ 3 : 1 5 u p $ s z q u p q f s j q i f s b m t $ s z q u p " 1 # q s f t d b m f s $ - , @ 5 u p 5 3 / ( 5 3 / ( e j w j t p s r g t @ d m l p v u r g t @ d m l p v u r g t @ d m l p v u r g t @ d m l p v u $ - , u p 3 5 & $ - , u p " % $ $ - , u p " ' & % ' & $ - , u p 3 5 $ d p s f . $ 0 . $ 0 q s f t d b m f s % & # 6 ( . * 4 $ . $ 0 @ $ - , @ $ ' ( r g t @ d m l p v u < > . * 4 $ 5 3 / ( @ 3 / $ - , @ $ ' ( @ 3 & ( 3 / ( $ - , @ 4 & - 4 : 4 5 @ $ 4 3 $ - , 4 0 6 3 $ & " . description stcom 24/58 docid028515 rev 1 at a startup the 24 mhz oscillator clock is select ed. this source must be always present to allow the stcom starting correctly. 24 mhz can be provided by a quartz crystal or by any other source. in this latter case, the clock must be provided through the mclk_in pin while the mclk_out pin must be tied to dgnd . 32.768 khz must be provided by a quartz crystal. apb peripherals can work up to 48 mhz. each pclk prescale r to the sub-s ystems should be configured to respect this maximum frequency. the general purpose adc clock can run up to 33 mhz. the rtc core uses only the 32 khz external oscillator. the trng can work with the external 32 khz or with the internal cpu_hclk. if the internal clock is selected, the divisor should be configured to provide an accurate 32 khz clock in order to respect the requirements for a true random generation. one master clock output line can be enabled. the mco1 is multiplexed with one general purpose i/o and can take one of the qfs outputs with a configurable prescaler. 1.8 power management the stcom should be powered with, at least, two external supply voltages: ? 3.3 v for i/os, embedded flash, qfs, dac, osc, adc general purpose, 1.2 v regulator ? 8 - 18 v for line driver the device needs also two more supply voltages that can be generated internally: ? 1.2 v for digital cores and logic, embedded flash, qf s and oscillator ? 5 v for the plc afe 1.2 v and 5 v can be provided by two internal linear regulators connected respectively to dvdd_1v2 and avdd_5v pins and supplied respectively by dvdd_3v3_reg and pvcc pins. a bypass mode is available for the 1.2 v regulator in case an external source is used. the power-on reset (por) is conditioned by th e level of dvdd_3 v3_io and dvdd_1v2: at power on, the whole stcom device is kept un der reset until the two supply voltages are above the respective turn-on thresholds named v(dvdd_3 v3_io)_th and v(dvdd_1v2)_th, while the device is turned off as soon as one of the voltages goes below its turn-off thresholds, namely v(dvdd_3 v3_io)_tl and v(dvdd_1v2)_tl. an internal comparator checks the supply voltage on avdd_5v_afe as well, enabling the use of the plc afe when the voltage is above v(avdd_5v_afe)_th and disabling it when the voltage goes below v(avdd_5v_afe)_tl. refer to figure 5 and figure 6 for the detailed power supply scheme. docid028515 rev 1 25/58 stcom description 58 figure 5. power supply scheme - digital section 7 # " 5 1 p x f s t x j u d i 3 5 $ d p s f c b d l v q s f h j t u f s t $ p s u f y . q f s j q i f s b m t 3 " . 3 f b m u j n f f o h j o f * 0 - p h j d - f w f m 4 i j g u f s t % 7 % % @ 7 @ 3 & ( 7 s f h v m b u p s % 7 % % @ 7 @ * 0 % 7 % % @ 7 ( 1 * 0 t % 7 % % @ 7 @ 2 ' 4 2 ' 4 % 7 % % @ 7 @ ' - " 4 ) % 7 % % @ 7 @ ' - " 4 ) % 7 % % @ 7 @ 2 ' 4 . ) [ p t d j m m b u p s % 7 % % @ 7 @ . $ - , u p 7 7 ' m b t i 7 t f d u j p o " . description stcom 26/58 docid028515 rev 1 figure 6. power supply scheme - plc afe and line driver section 3 9 & & 9 u h j x o d w r u $ 9 ' ' b 9 $ 9 ' ' b 9 b 3 * $ $ 9 ' ' b 9 b 5 ; $ ' & $ 9 ' ' b 9 b 7 ; ' 5 9 $ ) ( w r 9 3 9 & & 3 * 1 ' 3 * 1 ' $ * 1 ' 3 $ 3 $ $ 9 ' ' b 9 b ' $ & 9 ) h u u l w h e h d g $ 0 docid028515 rev 1 27/58 stcom description 58 vbat operation in case the rtc peripheral is used, the vbat pin shall be supplied (2.0 v to 3.6 v) for the rtc core operation and persistence of backup registers. an external battery or a similar power source can be used. the vbat operation is activated, through an on-chip power switch, when the dvdd_3v3_io is not present. in this case the main core of the rtc and the backup registers are under the vbat domain. the application can constantly monitor the health of the battery by reading the voltage level present at the vbat pin through the channel 7 of the general purpose 12-bit adc. a dedicated cutoff switch has been included to avoid continuous leakage from the battery when the adc is not sampling the line. 1.9 low power modes a clock gating is available for any peripheral in order to save all the dynamic power contributes related the resources not used by the application. the cpu is able to run at maximum frequency bu t, in case lower speed is sufficient to meet the application requirements, also scaled values are allowed. the cpu could be in low power modes waiting for wake-up events. 1.10 real-time clock (rtc ) and backup registers the stcom embeds an integrated real-time clock (rtc). the rtc provides a hardware calendar implementation, instead of a simple 32-bit free-running counter. the calendar can be initialized to set the current time/date of the system and prov ide information on sub- seconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. software can program the daylight saving comp ensation; it can control two programmable alarms (with interrupt function) that can be triggered by any combination of the calendar fields. synchronization can be done with an extern al clock using the sub- second shift feature. rtc maskable interrupts/events are: ? alarms: two alarms are present ? timestamps: two timestamps are present ? tamper: two tamper detection inputs are present the rtc is clocked with a 32.768 khz external crystal and has coarse calibration (periodic digital calibration), smooth calibration (0.954 ppm) and analog calibration functionalities.the 1 hz /512 hz internal reference clock is optionally available on rtc_tampb for calibration. the rtc has also twenty 32-bit backup registers (80 bytes), available for user defined data storage. the possibility that ba ckup registers are reset when a tamper detection event occurs is selectable by software. description stcom 28/58 docid028515 rev 1 1.11 temperature sensors an d overtemperature protection the stcom embeds an overtemperature protection mechanism, with fixed temperature threshold, preventing the device from overh eating. this automati c protection acts by shutting down the plc line driver when overheating occurs during plc transmission. the normal operation of the line driver is restor ed automatically as the overtemperature event has ended. in addition to the overtemperature automatic protection, information from two temperature sensors is provided: ? the line driver temperature sensor ? the low power temperature sensor the first sensor monitors the line driver temper ature and can be used by the rte to prevent the line driver to be shut down abruptly by the overtemperature protection. the way to use this information may depend on the protocol a nd on the version of the rte firmware, so its usage (if any) will be described within the sp ecific firmware documentation released by stmicroelectronics ? . the second sensor monitors the temperature of the low power section of the device. it is internally connected to the channel 8 of the general purpose 12-bit adc (see section : general purpose analog-to-digital converter (adc) on page 19 for further details) and it can be used by the application for its own purposes. the accuracy of the sensors is guaranteed by design. in case a higher accuracy is required on the low power temperature sensor, the user shall adopt its own calibration procedure during the application manufacturing. 1.12 boot modes the stcom provides different security levels of protection: 1. level 1: unsecure the cortex?-m4 is accessible through the jtag and it's possible to download the firmware in the embedded flash using debugger plug-in or to load it from the external nvm using the system boot functionality. it's also possible to download customer otp data such as cryptography keys. the shadow sector is not accessible. 2. level 2: secure the jtag is blocked and it's not possible to access the embedded flash for external read or write operation. it's possible to load the ciphered firmware image from the external nvm and upgrade the firmware thanks to the iap functionality. read access to the embedded flash is possible to the cortex tm -m4 code, including the shadow sector. 3. level 3: secure and locked the jtag is blocked and it's not possible to access the embedded flash for external read or write operation. some embedded fl ash sectors are locked. it's possible to upgrade the firmware thanks to the iap functionality unless the new image tries to change a locked area. read access to the embedded flash is possible to the cortex tm -m4 code, including the shadow sector. docid028515 rev 1 29/58 stcom description 58 4. level 4: secure for customer loader the jtag is blocked and it is not possible to access the embedded flash for the external read or write operation via the jtag, while the read and write access is allowed to the cortex tm -m4 code (with the exception of the shadow sector). with respect to the level 2, there is no load or upgrade of the firmware image from the external nvm. the firmware image shall be already present in the embedded flash (loaded in level 1) and a customer application (secondary bootloader) can manage upgrades. 5. level 1*: secure erase and unlocking the cortex?-m4 is accessible through the jtag and it's possible to download firmware in the embedded flash. before t he unlocking, the embedded flash is fully erased including the customer otp data. the shadow sector is not accessible. in order to respect these security requirements, the stcom embeds a bootloader code. the user can also configure the boot mode thro ugh the boot0/1 pins to select the proper mode. the following boot modes are available: 1. normal mode: this is the standard way of boot ing the code and eventually load (or restore) a new image version from the external nvm. 2. customer otp write mode: in this mode the user can write its security keys and data (e.g.: custom eui48). after booting in this mode the security level is 2 (secure) or 4 (secure for customer loader) based on the selected option. in the security level 2 only ciphered firmware can be loaded from an external memory while in the security level 4 the firmware upgrade is left to a customer bootloader. 3. unlocking mode: this is the boot mode that enables again all the debug feature. 4. low power mode: the minimal boot mode to guarantee low power operations. the rte is not enabled and the cortex tm -m4 code is executed as soon as possible at 24 mhz (the user can then scale the clock up or down). the relationship between the security level and boot mode are shown in table 5 : table 5. boot mode and se curity level relationship boot mode level 1 level 2 level 3 level 4 level 1* normal mode yes yes if lock option selected for some area go to level 3 yes, but no update is performed on locked sector yes (no update is performed) yes customer otp write mode yes go to level 2 or 4 no no no no unlocking mode yes go to level 1* yes go to level 1* yes go to level 1* yes go to level 1* yes go to level 1* low power mode yes yes yes yes yes description stcom 30/58 docid028515 rev 1 table 6 shows the values of the boot pins for each boot mode. 1.13 system reprogrammability the stcom supports both in-system and in-application programming (isp and iap) modes through the use of the embedded flash and an external non-volatile memory (nvm). if the external nvm contains two firmware copies, it's also possible to roll back to the previous firmware version in case of firmware malfunctioning. the change of firmware to enable different functionalities will requ ire a complete reset of the dev ice if the customer does not implement its own bootloader. 1.13.1 in-system programming (isp) the isp mode allows the user to erase and program the embedded flash through the jtag port. this mode can be inhibited to enhance the security level of the device. 1.13.2 in-application programming (iap) the iap mode allows the application on board to store in an external non-volatile memory the firmware to be downloaded into the internal embedded flash. the firmware image in the nvm is copied into the internal embedded flas h at the power-on. the boot code inside the device takes care of the inte grity check, embedded flash erasure and programming. iap can be done using the power line or by the local upgrade port. the customer can also write its dedicated bootloader to perform iap with t he activation of a specific security level. table 6. boot modes and boot0/1 pin values boot mode boot mode value boot1 boot0 normal boot 0x2 1 0 customer otp write 0x0 0 0 unlocking 0x1 0 1 low power 0x3 1 1 docid028515 rev 1 31/58 stcom pinout and pin description 58 2 pinout and pin description 2.1 pin definition figure 7. tqfp176 pinout ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ * 0 ( 1 * 0 @ 6 4 " 3 5 @ 3 9 % 6 4 " 3 5 @ 5 9 % 4 1 * @ 4 4 o 4 1 * @ 4 $ - , 4 1 * @ . * 4 0 4 1 * @ . 0 4 * % 7 % % @ 7 @ ' - " 4 ) % ( / % % 7 % % @ 7 @ ' - " 4 ) 3 & 4 & 3 7 & % # 0 0 5 # 0 0 5 + 5 " ( @ 5 3 4 5 o + 5 " ( @ 5 % * + 5 " ( @ 5 . 4 + 5 " ( @ 5 $ , + 5 " ( @ 5 % 0 % 7 % % @ 7 @ . $ - , % 7 % % @ 7 @ * 0 . $ - , @ * / . $ - , @ 0 6 5 % 7 % % @ 7 @ 3 & ( % 7 % % @ 7 % 7 % % @ 7 @ 2 ' 4 % 7 % % @ 7 @ 2 ' 4 % ( / % " 7 % % @ 7 @ 1 ( " 3 9 @ * / / 3 9 @ * / 1 " ( / % ; $ @ * / " ( / % " 7 % % @ 7 @ " ' & 1 7 $ $ 1 ( / % 1 " @ 0 6 5 1 " @ 0 6 5 1 " @ 0 6 5 1 " @ 0 6 5 1 ( / % 1 7 $ $ 1 " @ * / / 1 " @ * / 1 1 " @ * / 1 1 " @ * / / " ( / % $ 4 ' " 7 % % @ 7 3 & 4 & 3 7 & % " ( / % 5 9 % 3 7 @ 0 6 5 1 5 9 % 3 7 @ 0 6 5 / " 7 % % @ 7 @ 5 9 % 3 7 " 7 % % @ 7 @ % " $ " ( / % % " $ @ 0 6 5 1 % " $ @ 0 6 5 / % 7 % % @ 7 @ * 0 ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ 3 & ( % 7 % % @ 7 3 & 4 & 5 o ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ * 0 / $ / $ / $ / $ / $ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ * 0 ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ " % $ @ 7 3 & ' 1 " % $ @ 7 3 & ' / 0 4 $ @ * / 0 4 $ @ 0 6 5 % 7 % % @ 7 @ * 0 7 # " 5 3 5 $ @ 5 " . 1 " 3 5 $ @ 5 " . 1 # / $ / $ / $ / $ / $ / $ / $ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ * 0 ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 % 7 % % @ 7 @ 3 & ( % 7 % % @ 7 @ * 0 3 & 4 & 3 7 & % ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ ( 1 * 0 @ % 7 % % @ 7 @ * 0 ( 1 * 0 @ 5 2 ' 1 & y q p t f e q b e e p x o " . pinout and pin description stcom 32/58 docid028515 rev 1 table 7. pin description pin pin name type (1) dir. (2) rs (3) description 1 gpio00_3 d i/o i general purpose i/o, spi1_mosi, at1_ch_1, fsmc_pcad_17 2 gpio00_2 d i/o i general purpose i/o, spi1_ss, at1_bkin, fsmc_pcad_18, usart0_sclk 3 gpio00_1 d i/o i general purpose i/o, usart0_cts, fsmc_pcad_19 4 dvdd_3 v3_io s i i i/o 3.3 v supply 5 gpio00_0 d i/o i general purpose i/o, usart0_rts, fsmc_pcad_20 6 usart0_rxd d i i usart0_rxd 7 usart0_txd d o i usart0_txd 8 spi0_ssn d od i spi0_ssn 9 spi0_sclk d o i spi0_sclk 10 spi0_miso d i i spi0_miso 11 spi0_mosi d o i spi0_mosi 12 dvdd_1v2_flash s i i embedded flash memory 1.2 v supply 13 dgnd s - - embedded flash memory ground 14 dvdd_3 v3_flash s i i embedded flash memory 3.3 v supply 15 reserved - - reserved, tie to dgnd 16 boot0 d i i boot mode selector pin 0 17 boot1 d i i boot mode selector pin 1 18 jtag_trstn d i i jtag test reset - active low 19 jtag_tdi d i i jtag test data input 20 jtag_tms d i i jtag test mode select input, swio 21 jtag_tck d i i jtag test clock input, swclk 22 jtag_tdo d o i jtag test data output, swv 23 dvdd_1v2_ mclk s i i 24 mhz oscillator 1.2 v supply 24 dvdd_3 v3_io s i i i/o 3.3 v supply 25 mclk_in a - - 24 mhz oscillator input 26 mclk_out a - - 24 mhz oscillator output 27 dvdd_3 v3_reg s i i 3.3 v input for the 1.2 v regulator 28 dvdd_1v2 s i/o i/o 1.2 v regulator output / external supply input 29 dvdd_1v2_qfs s i i qfs 1.2 v supply 30 dvdd_3 v3_qfs s i i qfs 3.3 v supply 31 dgnd s - - qfs ground 32 avdd_5v_pga s i i pga 5 v supply 33 rx_inn a i i pga negative input docid028515 rev 1 33/58 stcom pinout and pin description 58 34 rx_inp a i i pga positive input 35 agnd s - - pga ground 36 zc_in a i i zero crossing comparator input 37 zc_agnd_ref a i i zero crossing comparator ground reference - connect to agnd 38 avdd_5v_afe s i i plc afe 5 v supply + receiver adc supply 39 pvcc s i i pa supply 40 pgnd s - - pa ground 41 pa2_out a o o pa2 output 42 pa2_out a o o pa2 output 43 pa1_out a o o pa1 output 44 pa1_out a o o pa1 output 45 pgnd s - - pa ground 46 pvcc s i i pa supply / 5 v regulator input voltage 47 pa1_inn a i i pa1 inverting input 48 pa1_inp a i i pa1 non-inverting input 49 pa2_inp a i i pa2 non-inverting input 50 pa2_inn a i i pa2 inverting input 51 agnd s - - 5 v regulator ground 52 csf a i/o i/o current sense feedback 53 avdd_5v s i/o i/o 5 v regulator ou tput / external supply input 54 reserved - - - reserved - connect to agnd 55 agnd s - - transmission predriver ground 56 txdrv_outp a o o transmission predriver positive output 57 txdrv_outn a o o transmission predriver negative output 58 avdd_5v_txdrv s i i transmission predriver 5 v supply 59 avdd_3 v3_dac s i i transmission dac 3.3 v supply 60 agnd s - - transmission dac ground 61 dac_outp a o o transmission dac positive output 62 dac_outn a o o transmission dac negative output 63 dvdd_3 v3_io s i i i/o 3.3 v supply 64 gpio10_7 d i/o i general purpose i/o, usart4_sclk, at0_bkin, spi2_ssn, i2c2_scl 65 gpio10_6 d i/o i general purpose i/o, usart4_txd, at0_ch_1, spi2_sclk, i2c2_sda table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description pinout and pin description stcom 34/58 docid028515 rev 1 66 gpio10_5 d i/o i general purpose i/o, usart4_rxd, at0_ch_2, spi2_miso, i2c0_scl 67 gpio10_4 d i/o i general purpose i/o, usart4_cts, at0_ch_3, spi2_mosi, i2c0_sda 68 gpio10_3 d i/o i general purpose i/o, usart4_rts, at0_ch_4, usart3_cts, i2c2_smba 69 gpio10_2 d i/o i general purpose i/o, at0_chn_1, usart3_rts, i2c0_smba 70 gpio10_1 d i/o i general purpose i/o, at0_chn_2, usart3_rxd 71 gpio10_0 d i/o i general purpose i/o, at0_chn_3, usart3_txd 72 dvdd_3 v3_reg s i i 3.3 v input for the 1.2 v regulator 73 dvdd_1v2 s i/o i/o 1.2 v regulator output / external supply input 74 resetn d i/od i/od reset input, open drain output - active low 75 gpio09_7 d i/o i general purpose i/o, at0_etr, etm_swo, spi4_sclk 76 gpio09_6 d i/o i general purpose i/o, usart3_sclk, etm_data_3, spi4_miso 77 gpio09_5 d i/o i general purpose i/o, etm_data_2, spi4_mosi 78 gpio09_4 d i/o i general purpose i/o, etm_data_1, spi4_ssn 79 gpio09_3 d i/o i general purpose i/o, etm_data_0, usart2_cts 80 gpio09_2 d i/o i general purpose i/o, etm_clkout, usart2_rts 81 gpio09_1 d i/o i general purpose i/o, can1_rx, usart2_rxd 82 gpio09_0 d i/o i general purpose i/o, can1_tx, usart2_txd 83 dvdd_3 v3_io s i i i/o 3.3 v supply 84 n. c. - - - not connected 85 n. c. - - - not connected 86 n. c. - - - not connected 87 n. c. - - - not connected 88 n. c. - - - not connected 89 n. c. - - - not connected 90 n. c. - - - not connected 91 n. c. - - - not connected 92 n. c. - - - not connected 93 n. c. - - - not connected 94 n. c. - - - not connected 95 n. c. - - - not connected 96 rtc_tampb d i/o i tamper input b, rtc clock output table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description docid028515 rev 1 35/58 stcom pinout and pin description 58 97 rtc_tampa d i i tamper input a 98 vbat s i i 2.0 to 3.6 v battery supply input 99 dvdd_3 v3_io s i i i/o 3.3 v supply 100 osc32_out a - - 32 khz oscillator output 101 osc32_in a - - 32 khz oscillator input 102 adc_vrefn a i i general purpose adc negative reference voltage input 103 adc_vrefp a i i general purpose adc positive reference voltage input 104 gpio08_5 d i/o i general purpose i/o, a dc_mux_vin_5, spi3_ssn, usart2_sclk 105 gpio08_4 d i/o i general purpose i/o, adc_mux_vin_4, spi3_sclk 106 gpio08_3 d i/o i general purpose i/o, adc_mux_vin_3, usart1_cts, spi3_miso 107 gpio08_2 d i/o i general purpose i/o, adc_mux_vin_2, usart1_rts, spi3_mosi 108 gpio08_1 d i/o i general purpose i/o, adc_mux_vin_1, usart1_rxd, i2c1_scl 109 gpio08_0 d i/o i general purpose i/o, adc_mux_vin_0, usart1_txd, i2c1_sda, at1_etr 110 gpio07_7 d i/o i general purpose i/o, at1_chn_3, spi1_sclk 111 gpio07_6 d i/o i general purpose i/o, at1_chn_2, spi1_miso 112 gpio07_5 d i/o i general purpose i/o, at1_chn_1, spi1_mosi 113 gpio07_4 d i/o i general purpose i/o, at1_ch_4, spi1_ssn 114 gpio07_3 d i/o i general purpose i/o, at1_ch_3 115 gpio07_2 d i/o i general purpose i/o, at1_ch_2 116 gpio07_1 d i/o i general purpose i/o, at1_ch_1, can0_rx 117 gpio07_0 d i/o i general purpose i/o, at1_bkin, can0_tx 118 gpio06_7 d i/o i general purpo se i/o, spi4_ssn, etm_swo 119 gpio06_6 d i/o i general purpose i/o, spi4_sclk, etm_data_3 120 gpio06_5 d i/o i general purpose i/o, spi4_miso, etm_data_2 121 gpio06_4 d i/o i general purpose i/o, spi4_mosi, etm_data_1 122 gpio06_3 d i/o i general purpose i/o, usart3_cts, i2c1_scl, etm_data_0 123 gpio06_2 d i/o i general purpose i/o, usart3_rts, i2c1_sda, etm_clkout 124 gpio06_1 d i/o i general purpose i/o, usart3_rxd, i2c1_smba, i2c2_scl 125 gpio06_0 d i/o i general purpose i/o, usart3_txd, i2c2_sda 126 gpio05_7 d i/o i general purpose i/o, usart3_sclk, i2c2_smba table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description pinout and pin description stcom 36/58 docid028515 rev 1 127 gpio05_6 d i/o i general purpose i/o, usart0_cts 128 gpio05_5 d i/o i general purpose i/o, usart0_rts 129 gpio05_4 d i/o i general purpose i/o, mco1 130 dvdd_3 v3_io s i i i/o 3.3 v supply 131 gpio05_3 d i/o i general purpose i/o, fsmc_ebar_1 132 gpio05_2 d i/o i general purpose i/o, usart2_sclk, fsmc_ebar_0 133 gpio05_1 d i/o i general purpose i/o, usart2_rxd, spi2_ssn, fsmc_bln_0 134 gpio05_0 d i/o i general purpose i/o, usart2_txd, spi2_sclk, fsmc_bln_1 135 dvdd_3 v3_io s i i i/o 3.3 v supply 136 gpio04_7 d i/o i general purpose i/o, usart2_cts, spi2_miso, fsmc_pcda_0 137 gpio04_6 d i/o i general purpose i/o, usart2_rts, spi2_mosi, fsmc_pcda_1, mco1 138 gpio04_5 d i/o i general purpose i/o, fsmc_pcda_2 139 gpio04_4 d i/o i general purpose i/o, fsmc_pcda_3 140 gpio04_3 d i/o i general purpose i/o, fsmc_pcda_4 141 gpio04_2 d i/o i general purpose i/o, fsmc_pcda_5 142 gpio04_1 d i/o i general purpose i/o, fsmc_pcda_6 143 gpio04_0 d i/o i general purpose i/o, fsmc_pcda_7 144 gpio03_7 d i/o i general purpose i/o, spi3_ssn, fsmc_pcda_8 145 gpio03_6 d i/o i general purpose i/o, spi3_sclk, fsmc_pcda_9 146 gpio03_5 d i/o i general purpose i/o, spi3_miso, fsmc_pcda_10 147 gpio03_4 d i/o i general purpose i/o, spi3_mosi, fsmc_pcda_11, usart3_sclk 148 gpio03_3 d i/o i general purpose i/o, spi2_ssn, usart3_cts, fsmc_pcda_12 149 gpio03_2 d i/o i general purpose i/o, spi2_sclk, usart3_rts, fsmc_pcda_13 150 gpio03_1 d i/o i general purpose i/o, spi2_miso, usart3_rxd, fsmc_pcda_14 151 gpio03_0 d i/o i general purpose i/o, spi2_mosi, usart3_txd, fsmc_pcda_15 152 dvdd_1v2 s i/o i/o 1.2 v regulator output / external supply input 153 dvdd_3 v3_reg s i i 3.3 v input for the 1.2 v regulator 154 dvdd_3 v3_io s i i i/o 3.3 v supply 155 reserved - - - reserved - connect to dgnd table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description docid028515 rev 1 37/58 stcom pinout and pin description 58 156 gpio02_7 d i/o i general purpose i/o, at0_bkin, fsmc_lbar, usart4_sclk 157 gpio02_6 d i/o i general purpose i/o, at0_ch_1, fsmc_pcwen, usart4_txd 158 gpio02_5 d i/o i general purpose i/o, at0_chn_1, fsmc_pcoen, usart4_rxd 159 gpio02_4 d i/o i general purpose i/o, at0_ch_2, fsmc_pcad_0, usart4_cts 160 gpio02_3 d i/o i general purpose i/o, at0_chn_2, fsmc_pcad_1, usart4_rts 161 gpio02_2 d i/o i general purpose i/o, at0_ch_3, fsmc_pcad_2 162 gpio02_1 d i/o i general purpose i/o, at0_chn_3, i2c2_scl, fsmc_pcad_3 163 gpio02_0 d i/o i general purpose i/o, at0_ch_4, i2c2_sda, fsmc_pcad_4 164 gpio01_7 d i/o i general purpose i/o, at0_etr, i2c2_smba, fsmc_pcad_5, i2c1_smba 165 gpio01_6 d i/o i general purpose i/o, i2c1_scl, can1_rx, fsmc_pcad_6 166 gpio01_5 d i/o i general purpose i/o, i2c1_sda, can1_tx, fsmc_pcad_7 167 gpio01_4 d i/o i general purpose i/o, usart1_cts, can0_rx, fsmc_pcad_8 168 gpio01_3 d i/o i general purpose i/o, usart1_rts, can0_tx, fsmc_pcad_9 169 gpio01_2 d i/o i general purpose i/o, usart1_rxd, at1_etr, fsmc_pcad_10 170 gpio01_1 d i/o i general purpose i/o, usart1_txd, at1_chn_3, fsmc_pcad_11 171 gpio01_0 d i/o i general purpose i/o, i2c0_smba, at1_chn_2, fsmc_pcad_12, usart1_sclk 172 gpio00_7 d i/o i general purpose i/o, i2c0_scl, at1_chn_1, fsmc_pcad_13 173 gpio00_6 d i/o i general purpose i/o, i2c0_sda, at1_ch_4, fsmc_pcad_14 174 gpio00_5 d i/o i general purpose i/o, spi1_sclk, at1_ch_3, fsmc_pcad_15 175 dvdd_3 v3_io s i i i/o 3.3 v supply table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description pinout and pin description stcom 38/58 docid028515 rev 1 176 gpio00_4 d i/o i general purpose i/o, spi1_miso, at1_ch_2, fsmc_pcad_16 177 expad s - - exposed pad - dgnd 1. type: d = digital; a = analog; s = supply/ground. 2. direction: i = input; o = output; i/o = input/output, od = open drain. 3. reset status: i = input, i/o = input/output, o = output. table 7. pin description (continued) pin pin name type (1) dir. (2) rs (3) description docid028515 rev 1 39/58 stcom pinout and pin description 58 2.2 gpios multiplexing scheme in the stcom, peripherals are connected to i/os through a multiplexer. at a time one single peripheral can control the i/os. in this way, t here is no conflict between peripherals sharing the same i/o pins. thanks to a set of configuratio n registers, the user can select one of the 4 possible alternate functions for each pin as described in table 8 . table 8. gpios multiplexing scheme pin name selection: 000 selection: 001 selection: 010 selection: 011 gpio00_0 usart0_rts fsmc_pcad_20 gpio00_1 usart0_cts fsmc_pcad_19 gpio00_2 spi1_ss at1_bkin fsmc_pcad_18 usart0_sclk gpio00_3 spi1_mosi at1_ch_1 fsmc_pcad_17 gpio00_4 spi1_miso at1_ch_2 fsmc_pcad_16 gpio00_5 spi1_sclk at1_ch_3 fsmc_pcad_15 gpio00_6 i2c0_sda at1_ch_4 fsmc_pcad_14 gpio00_7 i2c0_scl at1_chn_1 fsmc_pcad_13 gpio01_0 i2c0_smba at1_chn_2 fsmc_pcad_12 usart1_sclk gpio01_1 usart1_txd at1_chn_3 fsmc_pcad_11 gpio01_2 usart1_rxd at1_etr fsmc_pcad_10 gpio01_3 usart1_rts can0_tx fsmc_pcad_9 gpio01_4 usart1_cts can0_rx fsmc_pcad_8 gpio01_5 i2c1_sda can1_tx fsmc_pcad_7 gpio01_6 i2c1_scl can1_rx fsmc_pcad_6 gpio01_7 at0_etr i2c2_smba fsmc_pcad_5 i2c1_smba gpio02_0 at0_ch_4 i2c2_sda fsmc_pcad_4 gpio02_1 at0_chn_3 i2c2_scl fsmc_pcad_3 gpio02_2 at0_ch_3 fsmc_pcad_2 gpio02_3 at0_chn_2 fsmc_pcad_1 usart4_rts gpio02_4 at0_ch_2 fsmc_pcad_0 usart4_cts gpio02_5 at0_chn_1 fsmc_pcoen usart4_rxd gpio02_6 at0_ch_1 fsmc_pcwen usart4_txd gpio02_7 at0_bkin fsmc_lbar usart4_sclk gpio03_0 spi2_mosi usart3_txd fsmc_pcda_15 gpio03_1 spi2_miso usart3_rxd fsmc_pcda_14 gpio03_2 spi2_sclk usart3_rts fsmc_pcda_13 gpio03_3 spi2_ss usart3_cts fsmc_pcda_12 gpio03_4 spi3_mosi fsmc_pcda_11 usart3_sclk pinout and pin description stcom 40/58 docid028515 rev 1 gpio03_5 spi3_miso fsmc_pcda_10 gpio03_6 spi3_sclk fsmc_pcda_9 gpio03_7 spi3_ss fsmc_pcda_8 gpio04_0 fsmc_pcda_7 gpio04_1 fsmc_pcda_6 gpio04_2 fsmc_pcda_5 gpio04_3 fsmc_pcda_4 gpio04_4 fsmc_pcda_3 gpio04_5 fsmc_pcda_2 gpio04_6 usart2_rts spi2_mosi fsmc_pcda_1 gpio04_7 usart2_cts spi2_miso fsmc_pcda_0 gpio05_0 usart2_txd spi 2_sclk fsmc_bln_1 gpio05_1 usart2_rxd spi2_ss fsmc_bln_0 gpio05_2 usart2_sclk fsmc_ebar_0 gpio05_3 fsmc_ebar_1 gpio05_4 mco1 gpio05_5 usart0_rts gpio05_6 usart0_cts gpio05_7 usart3_sclk i2c2_smba gpio06_0 usart3_txd i2c2_sda gpio06_1 usart3_rxd i2c1_smba i2c2_scl gpio06_2 usart3_rts i2c1_sda etm_clkout gpio06_3 usart3_cts i2c1_scl etm_data_0 gpio06_4 spi4_mosi etm_data_1 gpio06_5 spi4_miso etm_data_2 gpio06_6 spi4_sclk etm_data_3 gpio06_7 spi4_ss etm_swo gpio07_0 at1_bkin can0_tx gpio07_1 at1_ch_1 can0_rx gpio07_2 at1_ch_2 gpio07_3 at1_ch_3 gpio07_4 at1_ch_4 spi1_ss gpio07_5 at1_chn_1 spi1_mosi gpio07_6 at1_chn_2 spi1_miso gpio07_7 at1_chn_3 spi1_sclk table 8. gpios multiplexing scheme (continued) pin name selection: 000 selection: 001 selection: 010 selection: 011 docid028515 rev 1 41/58 stcom pinout and pin description 58 gpio08_0 adc_ch_0 usart1_txd i2c1_sda at1_etr gpio08_1 adc_ch_1 usart1_rxd i2c1_scl gpio08_2 adc_ch_2 usart1_rts spi3_mosi gpio08_3 adc_ch_3 usart1_cts spi3_miso gpio08_4 adc_ch_4 spi3_sclk gpio08_5 adc_ch_5 spi3_ss usart2_sclk gpio09_0 can1_tx usart2_txd gpio09_1 can1_rx usart2_rxd gpio09_2 etm_clkout usart2_rts gpio09_3 etm_data_0 usart2_cts gpio09_4 etm_data_1 spi4_ss gpio09_5 etm_data_2 1spi4_mosi gpio09_6 usart3_sclk etm_data_3 spi4_miso gpio09_7 at0_etr etm_swo spi4_sclk gpio10_0 at0_chn_3 usart3_txd gpio10_1 at0_chn_2 usart3_rxd gpio10_2 at0_chn_1 usart3_rts i2c0_smba gpio10_3 usart4_rts at0_ch_4 usart3_cts i2c2_smba gpio10_4 usart4_cts at0_ch_3 spi2_mosi i2c0_sda gpio10_5 usart4_rxd at0_ch_2 spi2_miso i2c0_scl gpio10_6 usart4_txd at0_ch_1 spi2_sclk i2c2_sda gpio10_7 usart4_sclk at0_bkin spi2_ss i2c2_scl table 8. gpios multiplexing scheme (continued) pin name selection: 000 selection: 001 selection: 010 selection: 011 memory map stcom 42/58 docid028515 rev 1 3 memory map figure 8. memory map y ' ' ' ' ' ' ' ' y ' ' ' ' y ' ' ' ' y ' ' ' ' y y ' y $ y ' y ' ' ' ' ' ' y & ' ' ' y # ' ' ' y & ' ' ' y y & y # y & y ' ' ' ' ' ' y % ' ' ' y " ' ' ' y % ' ' ' y y % y " y % y ' ' ' ' ' ' ' y $ ' ' ' y ' ' ' y $ ' ' ' y y $ y y $ y ' ' ' y # ' ' ' y ' ' ' y # ' ' ' y y " y y # y ' ' ' ' y ' ' ' y ' ' ' y " ' ' ' y y y y " y ' ' ' ' y ' ' ' y ' ' ' y ' ' ' y ' y y y y & ' ' ' y ' ' y ' ' ' y ' ' ' y y y y y ' ' ' ' y ' ' ' y ' ' ' y ' ' ' y $ y y y y # ' ' ' y ' ' ' y ' ' ' y ' ' ' y y y y y ' ' ' ' y ' ' ' y ' ' ' y ' ' ' y y y y y ' ' ' ' ' ' ' y ' ' ' y ' ' ' y ' ' ' y y y y y ' ' ' y ' ' ' y ' ' ' y ' ' ' y y y y y ' ' ' y ' ' ' y ' ' ' y y y ' ' ' ' y y ' ' ' ' y ' ' ' y y ' ' ' y y y ' ' ' y y ' ' ' ' y ' ' ' y y ' ' ' y y y ' ' ' y y ' ' ' ' ' ' ' y y ' ' ' y y ' ' ' y y y ' ' ' y ' ' ' ' ' y y y ' ' ' y 3 f t f s w f e 3 f t f s w f e $ p n 3 f t f s w f e ' 4 . $ # b o l ' 4 . $ # b o l 3 f t f s w f e $ s z q u p f ' - " 4 ) 3 f b e 8 s j u f 3 " . , 3 " . , 3 f t f s w f e $ p n # b t j d 3 f t f s w f e * 1 $ s f h t * 1 $ , # b t j d " ) # " 5 5 # b t j d " ) # % . " $ # b t j d " 1 # ' 4 . $ # b t j d " 1 # . * 4 $ # b t j d " 1 # f ' - " 4 ) # b t j d " 1 # 4 : 4 $ 5 3 - # b t j d " 1 # 3 5 $ 3 f t f s w f e $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 # b t j d " 1 # ( 1 5 # b t j d " 1 # ( 1 5 # b t j d " 1 # ( 1 5 $ 0 . " 1 # $ " / $ 0 . " 1 # 6 " 3 5 # b t j d " 1 # ( 1 5 # b t j d " 1 # ( 1 5 # b t j d " 1 # 8 8 % 0 ( # b t j d " 1 # ( 1 5 # b t j d " 1 # ( 1 5 # b t j d " 1 # ( 1 5 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # " 5 $ 0 . " 1 # " % $ $ 0 . " 1 # " 5 $ 0 . " 1 # 4 1 * $ 0 . " 1 # 4 1 * $ s z q u p " 1 # " & 4 3 f t f s w f e $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ 0 . " 1 # ( 1 * 0 $ s z q u p " 1 # $ 3 $ $ 0 . " 1 # ( 1 * 0 $ s z q u p " 1 # 6 4 " 3 5 $ s z q u p " 1 # * $ $ 0 . " 1 # 4 1 * $ 0 . " 1 # 4 1 * $ 0 . " 1 # 4 1 * $ 0 . " 1 # * $ $ 0 . " 1 # $ " / $ 0 . " 1 # 6 " 3 5 $ 0 . " 1 # 6 " 3 5 $ 0 . " 1 # * $ $ 0 . " 1 # 6 " 3 5 3 f t f s w f e $ s z q u p " 1 # 5 3 / ( $ s z q u p " 1 # 1 3 / ( " . docid028515 rev 1 43/58 stcom electrical characteristics 58 4 electrical characteristics 4.1 absolute maximum ratings table 9. absolute maximum ratings - voltage symbol parameter min. max. unit pvcc line driver supply voltage range pgnd -0.3 20 v avdd_5v 5 v internal regulator voltage range agnd -0.3 min. (5.5, pvcc +0.3) v avdd_5v_afe, avdd_5v_pga, avdd_5v_txdrv 5 v plc afe supply voltage range agnd -0.3 min. (5.5, pvcc +0.3) v avdd_3 v3_dac 3.3 v plc afe supply voltage range agnd -0.3 5.2 v dvdd_3 v3_io, dvd_3 v3_reg i/o supply voltage range gnd-0.3 5.2 v dvdd_3 v3_qfs 3.3 v qfs supply voltage range dgnd -0.3 5.2 v dvdd_1v2, dvdd_1v2_flash 1.2 v digital supply voltage range gnd -0.3 2.4 v dvdd_1v2_qfs 1.2 v qfs supply voltage range gnd -0.3 2.4 v adc_vrefp general purpose adc positive reference voltage range gnd -0.3 min. (5.2, dvdd_3v3_io + 0.3) v adc_vrefn general purpose adc negative reference voltage range gnd -0.3 min. (5.2, dvdd_3v3_io + 0.3) v vbat vbat voltage range gnd -0.3 5.2 v dgnd, agnd variations between different ground pins gnd -0.3 gnd +0.3 v pgnd variations between different ground pins agnd -0.3 agnd +0.3 v v(dig_in) input voltage range gnd -0.3 min. (5.2, dvdd_3v3_io + 0.3) v pa_out pa output pins voltage range pgnd -0.3 min. (20, pvcc +0.3) v pa_in pa input pins voltage range agnd -0.3 min. (20, pvcc +0.3) v rx_in rx_in input pins voltage range -5.5 9 v zc_in zc_in voltage range -5.5 min. (5.5, avdd_5v_ afe +0.3) v dac_out dac output pins voltage range agnd -0.3 min. (5.2, avdd_5v_ afe +0.3) v txdrv_out txdrv output voltage range agnd -0.3 min (. 5.5, avdd_5v_ afe +0.3) v csf csf pin voltage range agnd-0.3 avdd_5v +0.3 v v(mclk) 24 mhz oscillator pins voltage range gnd-0.3 min. (5.2, dvdd_3 v3_io+0.3) v electrical characteristics stcom 44/58 docid028515 rev 1 4.2 thermal characteristics v(osc32) 32 khz oscillator pins voltage range gnd-0.3 min. (5.2, dvdd_3v3_io + 0.3) v v(esd) maximum withstanding voltage range test condition: ansi-esda-jedec_js-001 ?human body model? acceptance criteria: ?normal performance? -2 +2 kv table 9. absolute maximum ratings - voltage (continued) symbol parameter min. max. unit table 10. absolute maximum ratings - current symbol parameter min. max. unit i(pa_out) pa repetitive rms current 1.5 a rms table 11. thermal characteristics symbol parameter conditions min. max. unit t(j) junction temperature 125 c t(amb) operating ambient temperature -40 85 c t(stg) storage temperature -50 150 c docid028515 rev 1 45/58 stcom electrical characteristics 58 4.3 operating conditions t(amb) = -40 to +85 c, t(j) < 125 c , pvcc = 18 v unless otherwise specified. all typical values are referred to t(amb) = 25 c. power supply characteristics table 12. analog supply characteristics symbol parameter (1) conditions min. typ. max. unit v(pvcc) line driver supply voltage 8 15 18 v i(pvcc)_rx line driver supply current rx mode no load on avdd_5v 500 ? a i(pvcc)_tx line driver supply current tx mode, no load no load on avdd_5v dual power amplifier configuration 40 ma no load on avdd_5v single power amplifier configuration 20 ma v(pvcc)_th line driver supply voltage turn-on threshold 7v v(pvcc)_tl line driver supply voltage turn-off threshold 6.5 v v(pvcc)_hyst line driver supply voltage hysteresis 0.5 v v(avdd_5v) 5 v regulator output voltage , no load 4.5 5 5.5 v v(avdd_5v_afe)_th 5 v plc afe supply voltage turn-on threshold 4.33 v v(avdd_5v_afe)_tl 5 v plc afe supply voltage turn-off threshold 4.26 v v(avdd_5v_afe)_hyst 5 v plc afe supply voltage hysteresis 60 mv i(5v)_rx 5 v plc afe supply current rx mode see (2) pga maximum gain 54 ma 5 v plc afe supply current rx active mode see (2) pga maximum gain rx in progress 61 ma i(5v)_tx 5 v plc afe supply current tx mode, no load see (2) 9ma i(avdd_3v3_dac) rx 3.3 v plc afe supply current rx mode 1.6 ma i(avdd_3v3_dac) tx 3.3 v plc afe supply current tx mode dac full scale current = 4 ma sine wave output f = 100 khz 6ma electrical characteristics stcom 46/58 docid028515 rev 1 symbol parameter (1) conditions min. typ. max. unit v(dvdd_3v3_io) digital i/o supply voltage 3.0 3.3 3.6 v v(dvdd_3v3_io)_th digital i/o supply voltage turn-on threshold 2.82 v v(dvdd_3v3_io)_tl digital i/o supply voltage turn-off threshold 2.7 v v(dvdd_3v3_io)_hyst digital i/o supply voltage hysteresis 0.1 v v(dvdd_3v3_reg) 1.2 v regulator input voltage 3.3 v v(dvdd_1v2) 1.2 v regulator output voltage low power mode 1.233 v high power mode 1.285 v i(dvdd_1v2) 1.2 v regulator output current low power mode 15 ma high power mode 300 ma v(dvdd_1v2)_th 1.2 v supply voltage turn-on threshold low and high power modes 1.11 v v(dvdd_1v2)_tl 1.2 v supply voltage turn-off threshold low and high power modes 1.025 v v(dvdd_1v2)_hyst 1.2 v supply voltage hysteresis low power mode 86 mv high power mode 86 mv 1. based on characterization, not tested in production. 2. i(5 v) = i(avdd_5v_afe) + i(avdd_5v_pga) + i(avdd_5v_txdrv). table 12. analog supply characteristics (continued) table 13. digital supply characteristics - rte symbol parameter (1) conditions min. typ. max. unit i(dvdd_1v2) 1.2 v digital supply current rte frequency = 48 mhz see (2) 29 ma i(dvdd_1v2) 1.2 v digital supply current rte frequency = 120 mhz see (2) 68 ma 1. based on characterization, not tested in production. 2. the tests are performed with the following enabled digital blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng, qfs. cortex? frequency equals to 48 mhz and cortex? fetc hing by ram. the value is calculated by measuring the difference in the supply current with and without rte enabled and running. docid028515 rev 1 47/58 stcom electrical characteristics 58 table 14. digital supply characteristics - cortex?-m4 fetching from ram symbol parameter conditions min. typ. max. unit i(dvdd_1v2) 1.2 v digital supply current cortex? frequency = 24 mhz see (1) 9.6 ma i(dvdd_3v3) 3.3 v digital supply current cortex? frequency = 24 mhz see (1) 0.9 ma i(dvdd_1v2) 1.2 v digital supply current cortex? frequency = 48 mhz see (1) 16.4 ma i(dvdd_3v3) 3.3 v digital supply current cortex? frequency = 48 mhz see (1) 0.9 ma i(dvdd_1v2) 1.2 v digital supply current cortex? frequency = 72 mhz see (1) 23.8 ma i(dvdd_3v3) 3.3 v digital supply current cortex? frequency = 72 mhz see (1) 0.9 ma i(dvdd_1v2) 1.2 v digital supply current cortex? frequency = 96 mhz see (1) 30.9 ma i(dvdd_3v3) 3.3 v digital supply current cortex? frequency = 96 mhz see (1) 0.9 ma 1. all the tests are performed with the following enabled digita l blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng, qfs. table 15. digital supply characteristics - cortex?-m4 fetching data from eflash symbol parameter conditions min. typ. max. unit i(dvdd_1v2) 1.2 v digital supply current cortex? frequency = 24 mhz see (1) 11.2 ma i(dvdd_3v3) 3.3 v digital supply current cortex? frequency = 24 mhz see (1) 3.5 ma i(dvdd_1v2) 1.2 v digital supply curr ent cortex? frequency = 48 mhz see (1) 17.6 ma i(dvdd_3v3) 3.3 v digital supply curr ent cortex? frequency = 48 mhz see (1) 3.6 ma i(dvdd_1v2) 1.2 v digital supply curr ent cortex? frequency = 72 mhz see (1) 24.2 ma i(dvdd_3v3) 3.3 v digital supply curr ent cortex? frequency = 72 mhz see (1) 3.7 ma i(dvdd_1v2) 1.2 v digital supply curr ent cortex? frequency = 96 mhz see (1) 30.6 ma i(dvdd_3v3) 3.3 v digital supply curr ent cortex? frequency = 96 mhz see (1) 3.8 ma 1. all the tests are performed with the following enabled digita l blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng, qfs. table 16. digital supply characteris tics - doze (sleep)/deepsleep mode symbol parameter condi tions min. typ. max. unit i(dvdd_1v2) 1.2 v digital supply current cortex? in doze mode see (1) 6.5 ma i(dvdd_3v3) 3.3 v digital supply current cortex? in doze mode see (1) 0.9 ma i(dvdd_1v2) 1.2 v digital supply current cortex? in deepsleep mode see (1) 6.5 ma i(dvdd_3v3) 3.3 v digital supply current cortex? in deepsleep mode see (1) 0.9 ma 1. the test is performed with the foll owing enabled digital blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng. electrical characteristics stcom 48/58 docid028515 rev 1 table 17. supply characteristics - qfs symbol parameter conditions min. typ. max. unit i(dvdd_1v2_qfs) qfs power consumption from 1.2 v power supply master clock = 24 mhz see (1) 5.1 ma i(dvdd_3v3_qfs) qfs power consumption from 3.3 v power supply master clock = 24 mhz see (1) 1.1 ma 1. the test is performed with the following enabled digita l blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng. the value is calculated by measuring the difference in the supply current with and without qfs enabled and running. table 18. 24 mhz oscillator symbol parameter conditions min. typ. max. unit f(mclk) crystal oscillator frequency 24 mhz c0 external quartz crystal shunt capacitance 3.5 pf esr external quartz crystal esr value see (1) 60 ? cl mclk_in , mclk_out load capacitance see (1) 10 15 pf 1. guaranteed by design, not tested in production. table 19. 32 khz oscillator symbol parameter conditions min. typ. max. unit f(osc32) crystal oscillator frequency 32.768 khz c0 external quartz crystal shunt capacitance 0.9 pf esr external quartz crystal esr value see (1) 60 k ? cl external quartz crystal load capacitance see (1) 12.5 pf 1. guaranteed by design, not tested in production. table 20. digital supply characteristics - i/o symbol parameter condi tions min. typ. max. unit i(dvdd_3v3_io) 3.3 v i/o digital supply current 8 gpio toggling at 0.5 mhz with cext ~= 50 pf see (1) 23.0 ma i(dvdd_3v3_io) 3.3 v i/o digital supply current 8 gpio toggling at 1 mhz with cext ~= 50 pf see (1) 24.9 ma i(dvdd_3v3_io) 3.3 v i/o digital supply current 8 gpio toggling at 8 mhz with cext ~= 50 pf see (1) 49.4 ma 1. the tests are performed with the following enabled digital blocks: 2 x gpt, 2 x spi, 2 x usart, ipc, dma, 2 x i 2 c, aes, trng, qfs. cortex? frequency equals to 96 mhz and cortex? fetc hing by ram. the values are calculated by measuring the difference in the supply current with and without 8 gpios enabled and toggling at the given frequency. docid028515 rev 1 49/58 stcom electrical characteristics 58 table 21. i/o characteristics symbol parameter (1) conditions min. typ. max. unit i (i/o) output current sunk by any i/os and control pin see (1) 8 ma output current source by any i/os and control pin see (1) 8 1. guaranteed by design, not tested in production. table 22. digital supply characterist ics - power consumption under battery symbol parameter conditions min. typ. max. unit i(dvdd_vbat) digital supply current under v bat 1.3 ? a electrical characteristics stcom 50/58 docid028515 rev 1 4.4 plc analog front-end (afe) and line driver characteristics 4.4.1 line driver characteristics table 23. line driver characteristics symbol parameter conditions min. typ. max. unit v(pax_out) bias power amplifier output bias voltage - rx mode pvcc/2 v gbwp power amplifier gain-bandwidth product 149 mhz i(pax_out) max power amplifier maximum output current 1000 ma rms v(pax_out) hd2 power amplifier output 2 nd harmonic distortion vcc = 18 v, v(pa_out) = 13 vpp, rload = 50 ? , f = 100 khz v(pa_out) dc = pvcc/2 -64 dbc v(pax_out) hd3 power amplifier output 3 rd harmonic distortion -67 dbc v(pax_out) thd power amplifier output total harmonic distortion -61 db v(pax_out) hd2 power amplifier output 2 nd harmonic distortion vcc = 18 v, v(pa_out) = 13 vpp, rload = 50 ? , f = 500 khz v(pa_out) dc = pvcc/2 -57 dbc v(pax_out) hd3 power amplifier output 3 rd harmonic distortion -58 dbc v(pax_out) thd power amplifier output total harmonic distortion -54 db c(pax_inp), c(pax_inn) power amplifier input capacitance pa_in+ vs. vss (see (1) )10pf pa_in- vs. vss (see (1) )10pf psrr power supply rejection ratio 50 hz -100 db 1 khz -88 db csf_ratio ratio between pa_out and csf output current 106 1. not tested in production, guaranteed by design. docid028515 rev 1 51/58 stcom electrical characteristics 58 4.4.2 line driver test circuit figure 9. line driver test circuit 4.4.3 afe characteristics transmission path characteristics & 6 , * 1 $ / , 1 3 $ [ b , 1 3 5 b / 2 $ ' 3 $ [ b 2 8 7 3 $ [ b , 1 1 & q ) 5 5 5 5 9 & & & q ) $ 0 table 24. dac characteristics symbol parameter conditions min. typ. max. unit i(dac_out) current dac output current rx mode, current measured on both outputs 0ma i(dac_out) current dac output current tx mode, current measured on both outputs 4ma v(dac_out) tx mode, differential rload = 120 ?? 1% 1 vpp v(dac_out) hd2 dac output 2 nd harmonic distortion r(dac_out) = 120 ? fclk = 20 mhz fout = 100 khz -76 dbc v(dac_out) hd3 dac output 3 rd harmonic distortion -83 dbc v(dac_out) thd dac output total harmonic distortion -74 dbc v(dac_out) hd2 dac output 2 nd harmonic distortion r(dac_out) = 120 ? fclk = 20 mhz fout = 500 khz -74 dbc v(dac_out) hd3 dac output 3 rd harmonic distortion -82 dbc v(dac_out) thd dac output total harmonic distortion -73 dbc electrical characteristics stcom 52/58 docid028515 rev 1 reception path characteristics table 25. predriver characteristics symbol parameter conditions min. typ. max. unit v(tx_out) bias transmitter output bias voltage rx mode avdd_5v_txdrv/2 v - predriver load impedance 1 k ? v(tx_out) hd2 transmitter output 2 nd harmonic distortion - see (1) v(tx_out) = 4.7 v pk-pk, no load, fout = 100 khz -76 dbc v(tx_out) hd3 transmitter output 3 rd harmonic distortion see (1) -83 dbc v(tx_out) thd transmitter output total harmonic distortion see (1) -74 db v(tx_out) hd2 transmitter output 2 nd harmonic distortion - see (1) v(tx_out) = 4.7 v pk-pk, no load, fout = 500 khz -74 dbc v(tx_out) hd3 transmitter output 3 rd harmonic distortion see (1) -82 dbc v(tx_out) thd transmitter output total harmonic distortion see (1) -73 db 1. dac + predriver chain distortion. table 26. receiver in put referred noise symbol parameter conditions min. typ. max. unit v(rx_inp - rx_inn) receiver input referred noise cenelec-a (35 khz to 95 khz) 16 dbv cenelec -b (95 khz to 125 khz) 12 dbv cenelec -c (125 khz to 140 khz) 8 dbv cenelec -d (140 khz to 148 khz) 5 dbv arib std-t84 (35 khz to 400 khz) 22 dbv fcc-low (35 khz to 125 khz) 17 dbv g3-fcc (150 khz to 490 khz) 21 dbv table 27. plc pga characteristics symbol parameter conditions min. typ. max. unit v(rx_inp), v(rx_inn) receiver input maximum voltage single-ended mode 10 v p-p v(rx_inp- rx_inn) receiver input maximum voltage differential mode 20 v p-p - receiver input bias voltage avddd_5 v_pga/2 v - receiver input impedance 5.2 k ? docid028515 rev 1 53/58 stcom electrical characteristics 58 zero crossing comparator characteristics gpga(plc) plc pga minimum gain -12 db plc pga maximum gain 42 db gpga(plc)_step plc pga gain step 6 db table 27. plc pga characteristics symbol parameter conditions min. typ. max. unit table 28. adc characteristics parameter conditions min. typ. max. unit adc input range differential mode 5 v p-p resolution 12 bit table 29. zero crossing characteristics symbol parameter conditions min. typ. max. unit v(zc_in) max zero crossing detection input voltage range 10 v p-p v(zc_in) tl zero crossing detection input low threshold -6 mv v(zc_in) th zero crossing detection input high threshold +6 mv zc_in d.c. zero crossing input duty cycle 50 % zc_in delay mains zero crossing to detection delay time 5.8 ? s electrical characteristics stcom 54/58 docid028515 rev 1 4.5 embedded flash characteristics . table 30. flash memory characteristics symbol parameter (1) conditions min. typ. (2) max. (3) max. (4) unit t dwprg double word program not including sw overhead 18 50 500 ? s t mprg module program (512 kb) not in cluding sw overhead 1.3 1.65 33 s t bkprg bank program (1056 kb) not including sw overhead 2.6 6.6 66 s t er16k sector pre-program and erase (16 kb) 0.2 0.5 5.0 s t er32k sector pre-program and erase (32 kb) 0.3 0.6 5.0 s t er64k sector pre-program and erase (64 kb) 0.4 0.9 5.0 s t er128k sector pre-program and erase (128 kb) 0.6 1.3 5.0 s t mker module erase (512 kb) 4.8 7.6 55 s t bker bank erase (1056 kb) 8 12.6 91 s t pabt program abort latency - 10 10 ? s t eabt erase abort latency - 30 30 ? s t esus erase suspend latency - 30 30 ? s t esrt erase suspend request rate 20 - - - ms 1. based on characterization, not tested in production. 2. assuming nominal supply values and operation at 25 c, 0 cycles. 3. assuming nominal supply values and operation at 25 c, 100 cycles. 4. assuming nominal supply values and operation at 125 c, 100 kcycles. table 31. flash memory endurance and data retention symbol parameter conditions min. (1) typ. max. unit n end endurance ta = -40 to +85 c 1 k cycles t ret data retention 1 kcycle at ta = +85 c (2) 15 years 1 kcycles (2) at ta = +55 c (see (2) ) 30 years 1. based on characterization, not tested in production. 2. cycling performed over the whole temperature range. table 32. flash memory current consumption symbol parameter conditions min. typ. max. unit i(flash_vdd3v3) current consumption from 3.3 v supply source during the erase of all the sectors - see (1) 1.6 ma i(flash_vdd1v2) current consumption from 1.2 v supply source during the erase of all the sectors (1) 12.3 ma 1. during characterization, not tested in production. th e values exclude the consum ption from other pins. docid028515 rev 1 55/58 stcom package information 58 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark. 5.1 tqfp176 package information figure 10. tqfp176 (20 x 20 x 1 mm) package outline 7 4 ) 3 package information stcom 56/58 docid028515 rev 1 5.2 thermal data table 33. tqfp176 (20 x 20 x 1 mm) package mechanical data symbol dimensions (millimeters) min. typ. max. a 1.20 a1 0.05 0.127 a2 0.95 1.00 1.05 b 0.13 0.18 0.23 c 0.09 0.20 d 21.80 22.00 22.20 d1 19.80 20.00 20.20 d2 8.70 d3 17.20 e 21.80 22.00 22.20 e1 19.80 20.00 20.20 e2 8.70 e3 17.20 e0.40 l 0.45 0.60 0.75 l1 1.00 k 03.57 ccc 0.08 table 34. thermal data symbol parameter conditions typ. value unit r thja maximum thermal resi stance junction ambient steady state mounted on a 2s2p pcb, with a dissipating surface, connected through vias, on the bottom side of the pcb. 34 c/w docid028515 rev 1 57/58 stcom ordering information 58 6 ordering information 7 revision history table 35. ordering information order code package packing eflash size STCOM10 tqfp176 (20 x 20 x 1 mm) tray 1 mb stcom05 tqfp176 (20 x 20 x 1 mm) tray 640 kb table 36. document revision history date revision changes 15-oct-2015 1 initial release. stcom 58/58 docid028515 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
Price & Availability of STCOM10
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |